With an increasing of a device density of a very large scale integrated circuit and a scaling down of a feature size thereof, copper wiring and copper interconnection technologies are currently used for chip fabrication. Generally, at least four times of copper film deposition and a chemical mechanical polishing (CMP) process are required to fabricate a chip. A CMP process control requires extremely accurate and stable measurements of film thickness and morphology, and is an important step affecting the yield.
In order to optimize CMP process parameters, increase a CMP yield and improve a planarization effect, it is very important to obtain a global and accurate film thickness of a silicon wafer. Different process parameters may be used in CMP in accordance with different points or regions having different film thicknesses on the silicon wafer so as to achieve a global silicon wafer planarization and a good silicon wafer polishing uniformity. Moreover, different polishing process parameters may be used in CMP in accordance with different silicon wafers having different film thicknesses so as to ensure the polishing uniformity between different silicon wafers. Thus, accurate measurement of film thicknesses of various points on the silicon wafer is very important.